Design & Verification Engineer

& : * Chip level verification, / Methodology * // protocols and seeded * Exposure to any of these scripting language -perl/bash-shell/python * Have lots of debugging skills to quickly scan and identify issues in system verilog/Verilog,C-code * Good in tool usage for simulation (VCS),waveform debug(Verdi) Skills:- UVM and SV This is a short preview. Tap Apply to read the full job description and apply on the employer's or recruiter's page.