Engineer, Design Verification

Job Description Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off Define and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria Develop scalable, reusable UVM‑based verification environments for IP and subsystem verification Lead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics Apply AI/ML‑assisted verification … This is a short preview. Tap Apply to read the full job description and apply on the employer's or recruiter's page.