Lead Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design verification of ASICs for Palladium. Position is based in Bangalore Will have to work at IP, Sub-System and SOC level verification. Test plan creation, functional coverage plan and coding of functional coverage bins. Will be involved in post silicon validation/bring up. Job Requirements Strong expertise in Verilog, HVL( SV/Specman e) with UVM/OVM/eRM methodology. Experience in fu… This is a short preview. Tap Apply to read the full job description and apply on the employer's or recruiter's page.