Memory Layout Design Engineer

Job Description: Job Requirements: Minimum 8 years of experience with a Bachelor's degree or 6 years of experience with a Master's degree, strong layout knowledge. Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules). Strong layout knowledge in advanced submicron FinFET processes, including TSMC 5nm, 3nm, 2nm, A14 or Samsung lower FinFET nodes. Key Responsibilities: Understand and apply layout guidelines, new pro… This is a short preview. Tap Apply to read the full job description and apply on the employer's or recruiter's page.