Principal Engineer – Static Timing Analysis (STA)

Role Overview We are seeking a highly experienced Principal Engineer – STA to lead timing analysis and signoff activities for advanced ASIC/SOC designs. The role requires deep expertise in static timing analysis methodologies, timing closure strategies, and signoff convergence across complex multi-clock, multi-voltage, and high-performance designs. The ideal candidate will provide technical leadership, drive cross-functional collaboration, and enable successful tape-outs at advanced technology … This is a short preview. Tap Apply to read the full job description and apply on the employer's or recruiter's page.