Senior Digital Verification Engineer

Description We are looking for a highly motivated Senior Digital Verification Engineer with 5-7 years of experience in ASIC/SoC verification. The ideal candidate will have strong expertise in System Verilog (SV) and UVM , along with hands-on experience in developing scalable verification environments, coverage-driven verification, and debugging complex RTL and gate-level issues. Exposure to Gate-Level Simulation (GLS) is a plus LI-DJ1 Responsibilities Develop and execute comprehensive verificat… This is a short preview. Tap Apply to read the full job description and apply on the employer's or recruiter's page.