Staff/ Sr Staff/Principal Engineer, STA

Job Description We are seeking a seasoned Backend Design Expert specializing in Static Timing Analysis (STA) and Logic Synthesis . You will own the RTL-to-Gate conversion, constraint development, and final timing closure, ensuring our chips deliver maximum performance at the lowest possible power and area. Key Responsibilities Physical-Aware Synthesis and PPA optimization: Own and execute hierarchical synthesis flows to translate SystemVerilog RTL into optimized gate-level netlists. Execute phy… This is a short preview. Tap Apply to read the full job description and apply on the employer's or recruiter's page.